The present subject matter generally concerns multi-layer and cascade capacitors for use in a range of frequency applications including high frequency applications, and more particularly concerns multiple capacitor components provided in monolithic packages. The present subject matter utilizes interconnect and attachment features to create devices with improved and/or idealized performance characteristics, including high capacitance, low equivalent series inductance (ESL), and low or tunable equivalent series resistance (ESR).
The diversity of modern technical applications creates a need for efficient electronic components and integrated circuits for use therein. Capacitors are a fundamental component used for filtering, decoupling, bypassing and other aspects of such modern applications which may include wireless communications, alarm systems, radar systems, circuit switching, matching networks, and many other applications. A dramatic increase in the speed and packing density of integrated circuits requires advancements in decoupling capacitor technology in particular. When high-capacitance decoupling capacitors are subjected to the high frequencies of many present applications, performance characteristics become increasingly more important. Since capacitors are fundamental to such a wide variety of applications, their precision and efficiency is imperative. Many specific aspects of capacitor design have thus been a focus for improving the performance characteristics of capacitors.
The incredible variety of capacitor environments implies that capacitors are often subjected to a number of different operating frequencies. Many wireless communications systems, including satellite, GPS, and cellular applications, as well as high speed processor applications require capacitor technology that can accommodate high frequencies of operation. Examples of capacitor technology that are designed to accommodate a generally higher frequency range of operation are disclosed in U.S. Pat. No. 6,208,501 B1 (Ingalls et al.); U.S. Pat. No. 6,023,408 (Schaper); U.S. Pat. No. 5,886,867 (Chivukula et al.); U.S. Pat. No. 5,576,926 (Monsorno); and U.S. Pat. No. 5,220,482 (Takemura et al.). Capacitors are often designed either for such high frequency applications or for other lower frequency applications, but not both. Thus, a need exists for capacitors with diverse capabilities that are compatible with ideal operation over a wide range of frequencies. Examples of capacitors that may operate well in some limited range of frequencies can be found in U.S. Pat. No. 6,184,574 B1 (Bissey); U.S. Pat. No. 6,038,122 (Bergstedt et al.); and U.S. Pat. No. 5,786,978 (Mizuno).
Just as capacitors may be subjected to different frequencies of operation, so might they be subjected to different temperatures of operation. Acceptable performance at a given temperature often relates to the temperature coefficient of capacitance of the dielectric material used to form the capacitor. An existing technique that allows for desired capacitor operation at different temperatures involves stacking capacitors formed with different dielectric materials. Examples of this stacking technique can be found in U.S. Pat. No. 5,799,379 and U.S. Pat. No. 5,517,385 (Galvagni et al.).
An actual capacitor has an inherent resistance value that may not exist in a theoretical situation. This additional property of a capacitor is often referred to as equivalent series resistance (ESR). It is desired to create a capacitor that operates as close to theoretical operation as possible, and thus capacitors with low ESR are generally preferred. The need for minimal ESR is especially evident in decoupling capacitor applications. Increased ESR can increase the ripple voltage and power dissipation for a given capacitance value. This is related to the RC time constant of a capacitor and contributes to the need for low capacitor ESR. An example of a capacitor designed to offer low ESR is disclosed in U.S. Pat. No. 6,226,170 B1 (Nellison et al.).
Another way to achieve improved capacitor performance is by lowering the inductance of the device. Thus, it is preferred for decoupling capacitors to provide low equivalent series inductance (ESL) in order to maintain circuit efficiency. It may also be preferred to implement a capacitor design that reduces the self and mutual inductance of decoupling capacitors. U.S. Pat. No. 6,038,121 (Naito et al.) and U.S. Pat. No. 6,034,864 (Naito et al.) show exemplary capacitor configurations that are designed to cancel magnetic flux and reduce ESL.
Reducing the current path will lower self inductance. Since the current often has to travel the entire length of the capacitor, termination on the longer ends of the structure will reduce the current path. If the current in adjacent capacitor electrodes flows in opposite directions it will reduce the mutual inductance in a capacitor. Multiple terminations as utilized in interdigitated capacitor technology also lower the inductance value. U.S. Pat. No. 5,880,925 (DuPrxc3xa9 et al.) and U.S. Pat. No. 6,243,253 B1 (DuPrxc3xa9 et al.) disclose multilayer capacitors that offer some of the aforementioned lower inductance characteristics. The basic configuration discussed in these DuPrxc3xa9 patents corresponds to a type of multilayer capacitor hereafter referred to as an interdigitated capacitor (IDC).
Another approach to lowering the ESL of a decoupling capacitor is to minimize interconnect induction that results from termination configurations and mounting systems. Certain known termination schemes are characterized by high inductance and often prohibit very close spacing between components. Thus, an efficient termination scheme is desired that has low ESL and that facilitates high component density for integrated circuits. Thin film capacitor technology is used to provide exemplary capacitors for mounting on a substrate in U.S. Pat. No. 6,104,597 (Konushi) and U.S. Pat. No. 4,439,813 (Dougherty et al.).
Known termination schemes utilize electrode plates with hole arrangements therein to connect with internal columnar electrodes. Such arrangement provides a space-saving interconnect scheme with lowered ESL, but the hole arrangements in the capacitor electrodes reduce the overall capacitance of the structure by decreasing the effective area. An excess of these clearance holes can also contribute to shorting problems as the number of layers with them increases. An example of such a termination scheme can be found in European Patent Application 1,115,129 A2 (Ahiko and Ishigara.). Thus, a need exists for a termination scheme that provides low inductance as well as high capacitance.
There are many different performance characteristics of a capacitor for which improvement may be sought to facilitate desired operation. Selected of such characteristics as mentioned and discussed above may include low ESR, low ESL and other forms of inductance, high capacitance, broad frequency range of operation, efficient termination scheme and others. Achieving many or all of these desired characteristics in a single monolithic structure would thus facilitate a beneficial capacitive structure. While various aspects and alternative features are known in the field of capacitor technology, no one design has emerged that generally integrates all of the improved performance characteristics as discussed herein.
Exemplary background references in addition to those already cited in the specification include U.S Pat. No. 5,831,810 (Bird et al.); U.S. Pat. No. 5,811,868 (Bertin et al.); and U.S. Pat. No. 5,599,757 (Wilson et al.).
The disclosures of all the foregoing United States patents are hereby fully incorporated into this application by reference thereto.
The present subject matter recognizes and addresses various of the foregoing shortcomings, and others concerning certain aspects of capacitor technology. Thus, broadly speaking, a principal object of the presently disclosed technology is improved capacitor performance over a wide range of frequencies. More particularly, the disclosed multi-layer and cascade capacitor embodiments offer preferred operating characteristics and a variety of flexibility over a wide frequency range.
Another object of the present subject matter is to provide multiple components and corresponding advantages thereof in an integrated capacitor package. Varied combinations of the multiple components offers flexibility in the capacitor design and resulting performance. The integrated structure may provide a plurality of stacked capacitors arranged and interconnected in parallel.
Yet another object of the subject technology is to provide capacitor configurations that accommodate a wide range of operating conditions, including desired capacitance value and frequency of operation. Preferably, possible configurations can provide a capacitance range from 0.5 xcexcF to over 1 F and an operating frequency range from several KHz to several GHz.
A still further object of the presently disclosed technology relates to the ESR and ESL of the subject multi-layer and cascade capacitors. The embodiments disclosed herein are preferably characterized by both low ESL and low ESR. The ESR may also be tunable to a desired level in accordance with selected capacitor configurations and adjustable aspects thereof.
It is another object of the presently disclosed technology to provide a cascade capacitor whose stacked components are attached by advantageous interconnect features. Such attachment and interconnect features preferably offer low inductance and other advantages while maintaining a generally high capacitance value of the structure. The option of internal and/or external electrode connections in accordance with the present subject matter provides versatile termination configurations.
It is another object of the subject multi-layer and cascade capacitors to provide a monolithic structure that can be encapsulated in an epoxy molding to offer optional additional protection of the capacitor and any wire bonds or other connection means provided thereon.
It is yet another object of the present subject matter to optionally provide dielectric layers in multilayer portions of the subject cascade capacitor that have adjustable thickness. Different configurations can provide adjacent dielectric layers with varied thickness, thus broadening the resonance curve associated with a particular configuration.
Additional objects and advantages of the disclosed technology are set forth in, or will be apparent to those of ordinary skill in the art from, the detailed description herein. Also, it should be further appreciated by those of ordinary skill in the art that modifications and variations to the specifically illustrated, referenced, and discussed features and steps hereof may be practiced in various embodiments and uses of the disclosed technology without departing from the spirit and scope thereof, by virtue of present reference thereto. Such variations may include, but are not limited to, substitution of equivalent means and features, materials, or steps for those shown, referenced, or discussed, and the functional, operational, or positional reversal of various parts, features, steps, or the like.
Still further, it is to be understood that different embodiments, as well as different presently preferred embodiments, of this technology may include various combinations or configurations of presently disclosed features, steps, or elements, or their equivalents (including combinations of features or steps or configurations thereof not expressly shown in the figures or stated in the detailed description). A first exemplary embodiment of the present subject matter relates to a multi-layer capacitor comprising a substrate, a first electrode layer, a first insulating layer, and a second electrode layer provided in a successively stacked configuration. Electrically conductive vias are then also provided for electrical connection to selected portions of the electrode layers. The first and second electrode layers and the insulating layer all define respective pluralities of through-holes having respective diameters thereof through which the conductive vias may pass.
A variety of additional features may be incorporated with such first exemplary embodiment. One such feature corresponds to a resistive layer provided between the first insulating layer and the second electrode layer, wherein such resistive layer may also define a plurality of through-holes through which the conductive vias may pass. Yet another potential feature of such exemplary embodiment regards the substrate being characterized by an outer perimeter and the first and second electrode layers being characterized by respective substantially continuous portions and a plurality of tab portions extending from the respective continuous portions to the outer perimeter of the substrate. Still further optional features include additional insulating layers and/or solder balls attached to selected conductive vias.
A second exemplary embodiment of the present subject matter corresponds to a cascade capacitor comprising a first multi-layer capacitor, a second multi-layer capacitor and a plurality of electrically conductive lands coupling selected portions of the respective multi-layer capacitors. Each multi-layer capacitor is formed by a respective combination of electrode and insulating layers. Respective pluralities of tabs may extend from selected edges of the electrode layers. Selected layers of the first multi-layer capacitor may define through-holes through which conductive vias may pass to form electrical connections to certain electrode layers.
With further reference to such second exemplary embodiment of the disclosed technology, additional capacitors, such as for example a surface mount capacitor, a single layer capacitor, a double layer capacitor, an electro-chemical capacitor, a ceramic capacitor, a tantalum capacitor, and/or selected combinations thereof, may also be coupled to conductive lands of the cascade capacitor embodiment. In more particular embodiments, a plurality of cascade capacitors may be coupled to a common capacitor. Still further particular embodiments may be formed such that the thickness among distinct insulating layers of the second multi-layer capacitor in the cascade capacitor are varied to adjust the resonance characteristics of the device.
A third exemplary embodiment of the present subject matter concerns a multi-layer capacitor comprising a plurality of electrode layers and insulating layers stacked successively, a plurality of tabs extending from selected edges of respective electrode layers and exposed on selected sides of the multi-layer capacitor, a plurality of through-holes formed by and perforating the top-most electrode layer and the adjacent underlying insulating layer, a plurality of conductive vias passing through selected through-holes, and a plurality of electrically conductive lands coupling selected of the plurality of tabs. The tabs may preferably be arranged in an interdigitated fashion, and the through-holes are preferably formed to expose the next successive electrode layer of the multi-layer capacitor.
Additional embodiments of the present subject matter equally concern methodology in forming certain aspects of the disclosed multi-layer and cascade capacitor embodiments. A first exemplary embodiment of such methodology corresponds to a method for adjusting the equivalent series resistance (ESR) of a multi-layer component. The method may comprise such steps as producing a multi-layer component including at least first and second electrode layers separated by an insulating layer, providing a resistive layer between the insulating layer and one of the first or second electrode layers, and adjusting the ESR of the component by varying the effective resistance of the resistive layer. More particularly, the effective resistance may be varied by adjusting the composition or thickness of the resistive layer. Alternatively, the effective resistance may be varied by forming a plurality of through-holes perforating one of the electrode layers and by then adjusting the respective diameters of selected of the through-holes to vary the extent of coverage on the resistive layer.
A further exemplary embodiment of methodology in accordance with the present subject matter relates to a method of adjusting the resonance characteristics of a multi-layer component. Such method preferably comprises the steps of producing a multi-layer component having a plurality of successively stacked electrode layers, providing separate insulating layers sandwiched between each of the electrode layers, and varying the thickness among selected of the separate insulating layers whereby the resonance characteristics of the multi-layer component are adjusted. Such varying step may be accomplished for example with continuous thickness variation, with patterned thickness variation, and/or with matched variable thickness variation among layers.
Additional embodiments of the present subject matter, not necessarily expressed in this summarized section, may include and incorporate various combinations of aspects of features or parts referenced in the summarized objectives above, and/or features or parts as otherwise discussed in this application.
Those of ordinary skill in the art will better appreciate the features and aspects of such embodiments, and others, upon review of the remainder of the specification.